A power MOSFET normally requires considerable "silicon real estate" to perform power control and/or switching with a transistor. At the same time, low "on-resistance" is required for efficient device operation. Low specific "on-resistance" is also desirable because device cost is proportional to device area on the chip and lower on-resistance is usually achieved only by increasing the size of the device. Such transistors often require extensive isolation between adjacent devices and a large gate width to prevent source-drain shorting through various breakdown processes. The subject invention allows fabrication of a power MOSFET with reduced gate width, in part through use of a relatively deep gate oxide positioned adjacent to the source and drain regions. This achieves low specific "on-resistance", can be fabricated in general shape die areas, and has low associated production costs.